As integration of a semiconductor device increases, the gate length and the oxide layer thickness of an MOS transistor may decrease. In order to increase reliability of the MOS transistor and lower power consumption, a semiconductor device may have an internal voltage generator that lowers a voltage level of an external voltage to generate an internal voltage.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generator. In the internal voltage generator of FIG. 1, a mode determining portion 11 may determine whether a semiconductor device is in a normal mode or a deep power down mode in response to a deep power down signal PDPDE. The deep power down mode may be a technique used to prevent unnecessary power consumption in a semiconductor device which employs an internal voltage generator. When a semiconductor device enters the deep power down mode, an internal voltage Vint applied to an internal portion of a semiconductor device may be interrupted where an external voltage Vcc is applied to thereby prevent unnecessary power consumption. For example, in a semiconductor memory device such as a dynamic random access memory (DRAM), an internal voltage Vint supplied to a memory cell may be temporarily interrupted where data of a memory cell may not need to be retained.
A sleep mode applied to a portable semiconductor device may allow an internal voltage Vint to be supplied to a semiconductor device to maintain fundamental data, whereas the deep power down mode may start when data does not have to be retained and thus an internal voltage Vint applied to a semiconductor device may be interrupted.
The mode determining portion 11 may include a first inverter INV1 for inverting the deep power down signal PDPDE and a PMOS transistor PM for applying an external voltage Vcc to a first node Node1 in response to an inverted deep power down signal PDPDE. The first inverter INV1 may be driven by the external voltage Vcc and a ground voltage Vss, and the inverted deep power down signal PDPDE outputted from the first inverter INV1 may swing between the external voltage Vcc level and the ground voltage Vss level. The PMOS transistor PM may be turned on to apply the external voltage Vcc to the first node Node1 when the inverted deep power down signal PDPDE is at the ground voltage Vss level and may be turned off when the inverted deep power down signal PDPDE is at the external voltage Vcc level.
An internal voltage driving portion 12 may include driving PMOS transistors PD1 to PDn. In FIG. 1, the internal voltage driving portion 12 may include a plurality of driving PMOS transistors PD1 to PDn to supply a sufficient current to an internal portion of the semiconductor device, but if an electrical current consumed by the semiconductor device is sufficiently small, the internal voltage driving portion 12 may include only a single driving PMOS transistor. Also, even though a consumption current of the semiconductor device may be relatively large, the internal voltage driving portion 12 may still only include one large-scaled driving PMOS transistor, which may supply a large amount of current.
In FIG. 1, a plurality of driving PMOS transistors PD1 to PDn may be connected in parallel between the external voltage Vcc and an internal voltage node Node11 and may commonly receive a voltage level of the first node Node1 through their respective gates. Each of a plurality of driving PMOS transistors PD1 to PDn may selectively apply the external voltage Vcc to the internal voltage Vint through the internal voltage node Node11, in response to a voltage level of the first node Node1.
A comparator AMP may receive a reference voltage Vref through a negative terminal and the internal voltage Vint through a positive terminal and may adjust a voltage level of the first node Node1 in response to a voltage difference between the reference voltage Vref and the internal voltage Vint.
An operation of the conventional internal voltage generator of FIG. 1 is described below. The deep power down signal PDPDE may be applied at a low level to the internal voltage generator during a normal mode and may be applied at a high level to the internal voltage generator during the deep power down mode. The deep power down signal PDPDE applied to the internal voltage generator may be an input signal of the first inverter INV1, and so its low level may be the ground voltage Vss level and its high level may be the external voltage Vcc level. If the deep power down signal PDPDE of a low level is applied to the mode determining portion 11 during the normal mode of the semiconductor device, the first inverter INV1 may invert the deep power down signal PDPDE and may apply the inverted deep power down signal PDPDE at the external voltage Vcc level to the PMOS transistor PM. The PMOS transistor PM may be turned off in response to the inverted deep power down signal PDPDE at the external voltage Vcc level, and the first node may become a floating state.
The comparator AMP may receive the reference voltage Vref and the internal voltage Vint and may detect a voltage difference of the two voltages Vref and Vint. If the internal voltage Vint is lower than the reference voltage Vref, the comparator AMP may lower a level of the first node Node1. The driving PMOS transistors PD1 to PDn may selectively apply the external voltage Vcc to raise the voltage level of the internal voltage Vint, as applied to the internal voltage node Node11, in response to a voltage level of the first node Node1.
If a voltage level of the internal voltage Vint is higher than a voltage level of the reference voltage Vref, the comparator AMP may raise a voltage level of the first node Node1. The driving PMOS transistors PD1 to PDn may selectively apply the external voltage Vcc to lower the voltage level of the internal voltage Vint, as applied to the internal voltage node Node11, in response to a voltage level of the first node Node1.
The reference voltage Vref is a signal which may not be affected by a variation of the external voltage Vcc, the temperature and/or a manufacturing process. The reference voltage Vref may keep a constant level, and may be used to prevent the internal voltage Vint generated in the internal voltage generator from being changed by external factors. The comparator AMP and the driving PMOS transistors PD1 to PDn of the internal voltage driving portion 12 may form a feedback loop to suppress a variation of the internal voltage Vint according to a variation of an internal load of the semiconductor device.
When the semiconductor device is in the deep power down mode, the deep power down signal PDPDE may be applied at a high level to the internal voltage generator. The first inverter INV1 may invert the deep power down signal PDPDE, and may apply the inverted deep power down signal PDPDE at the ground voltage Vss level, to the PMOS transistor PM. The PMOS transistor PM may be turned on to apply the external voltage Vcc to the first node Node1 in response to the inverted deep power down signal PDPDE.
The driving PMOS transistors PD1 to PDn may be turned off in response to the external voltage Vcc of the first node Node1, the internal voltage node Node11 may become a floating state, and an electrical current may not flow to the internal portion of the semiconductor device.
In the conventional internal voltage generator, the driving PMOS transistors PD1 to PDn may be large-scaled to drive a large electrical current and have the very thin oxide layer in order to lower an operating point. However, the internal voltage generator which employs such driving PMOS transistors PD1 to PDn may have a problem in that a leakage current, such as a gate induced drain leakage, may occur in the deep power down mode.